Field of the Invention
This invention relates to logic circuit verification schemes and more particularly to schemes for analyzing time-oriented responses and signal delays through levels of proposed logic circuitry.
It is common practice to simulate a logic circuit prior to its fabrication in large-scale integrated circuitry. The logic circuitry can be conveniently modelled, modified and analyzed by computer prior to reducing the corrected circuitry to semiconductor processing techniques. The logic gates in a simulated logic circuit may be stimulated by applied signals to assure proper operation in accordance with the desired logic conditions. However, to assure proper operation of logic gates of the simulated logic circuitry, it is common to analyze signal delays over various paths to determine whether undesirable switching events are caused by signals that arrive at different times and appear as anomalous logic events which cause erroneous switching results.
Certain known simulators attempt to resolve timing errors by analyzing the operation of the simulated logic at time intervals substantially shorter than the normal clock-time operating intervals in order to identify dynamic conditions of signal delays and response times through the simulated logic that may be troublesome (see, for example, U.S. Pat. No. 4,527,249). Since only a minor portion of the gates in a typical logic circuit will change state in any given clock cycle, a substantial amount of testing is involved in these conventional schemes at sub-cycle operating intervals in order to identify the troublesome timing events. Other conventional timing analysis schemes simply accumulate the maximum or minimum delay values along a specified path for visual inspection.